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Electronic component manufacturers—are you ready for a new model for enhanced digital customer engagement and operational efficiency in electronics design? Say hello to PartQuest Design Enablement! Today we launch the PartQuest Design Enablement portfolio, a new, connected digital environment for electronic component manufacturers looking to scale smarter, more personalized and persistent engagement with their customers and prospects. Microchip Technology Inc. collaborated with us as an early adopter, leveraging the technology to streamline workflows and empower customers across the design journey. How can it help your business? ???? PartQuest Design Enablement transforms traditional, fragmented support and content experiences by delivering a persistent, data-driven environment that connects product discovery, interactive content, BOM intelligence, collaboration and digital support into one seamless journey. It empowers component manufacturers to turn every customer touchpoint into an opportunity for insight, enablement, and deeper engagement. “PartQuest Design Enablement represents a strategic leap forward in how electronic component manufacturers build digital relationships with their customers,” said AJ Incorvaia, our senior vice president. “By unifying design content, supply intelligence, collaboration and real-time analytics, PartQuest Design Enablement gives manufacturers like Microchip a powerful way to drive both operational efficiency and customer satisfaction at scale.” We unveiled the new software flow during Microchip MASTERs 2025, where Microchip Technology’s Chief Operating Officer, Rich Simoncic, highlighted PartQuest Design Enablement’s relevance to the future of customer experience in the electronics industry. “PartQuest Design Enablement represents a meaningful evolution in how we connect with and support the engineering community. Collaborating with Siemens on this initiative allows us to deliver a complete, intuitive customer experience that reflects how modern engineering teams operate. The collaboration demonstrates Microchip’s core strategy of delivering total system solutions by working closely with industry leaders to develop and improve embedded ecosystems.” At the event, we're showcasing how PartQuest Design Enablement streamlines the journey from idea to implementation, using Siemens tools, intelligent block-based design from CELUS, and Microchip’s design assets, with working boards of a classic electronic memory game using Microchip components available as take-home giveaways for attendees. For more information on PartQuest Design Enablement and its availability, check out the comments below. #DesignEnablement #EDA #ElectronicComponents

As chiplet-based architecture has become the foundation for next-generation AI, HPC, and data-centric systems, the need for a robust, open, and scalable interconnect standard has never been greater. With the release of the UCIe? 3.0 specification, the industry takes a major step forward—doubling bandwidth, enhancing power efficiency, alike continuous transmission protocols and emergency shutdown support. ?? Design teams are already exploring how to integrate these new capabilities into their chiplet-based systems. But with innovation comes comnd enabling new use cases plexity—especially in verification. That’s where Siemens EDA continues to play a pivotal role. ? We’re proud to be a trusted partner in the evolution of UCIe! ?? “Building on the long-standing relationship our Avery Verification IP team has with the UCIe standards body, and our collaboration with the leading innovators in UCIe semiconductor design, Siemens EDA is once again a key contributor for the newest version of UCIe technology,” said Gordon Allan, Director, Questa One Avery Verification IP at Siemens EDA. “We welcome this latest release of the UCIe solution from the UCIe Consortium, and we are seeing the impact this has already with our collaborations with leading edge users to build new, exciting applications across all markets for chiplet makers, integrators and foundry providers.” See the first comment for more information on UCIe 3.0 ??

We are absolutely thrilled to announce that our very own Oana Lazar, EDA embedded software engineer, has been named a winner in the prestigious Women's Engineering Society (WES) "Top 50 Women in Engineering (WE50) 2025" awards! ???? This year's WE50 theme, "Together We Engineer," celebrates women who are trailblazers, showcasing the powerful impact made by female engineers across diverse sectors like transport, construction, technology, and healthcare. These awards highlight individuals who have truly excelled in their field, making significant contributions to areas like digital health, decarbonization, heritage projects, space science, sustainability, and accessibility. ?? Oana's expertise and dedication in EDA embedded software engineering truly embody the spirit of these awards. Join us in congratulating Oana on this incredible and well-deserved recognition! ??

Last month at #62DAC we had the pleasure of hosting leading industry partners in a panel discussion about software-defined systems (SDS), what they mean for the automotive industry and how a paradigm shift is required in the supporting infrastructure. Arm is at the forefront of this shift, and Suraj Gajendra shared his thoughts from this discussion and explains how Arm are pivoting to support SDS and are preparing for AI-defined vehicles. Key takeaways: ?? Infrastructure first: SDVs need a comprehensive cloud-to-car ecosystem, built from day one, for continuous innovation ?? Virtual platforms accelerate: Arm is cutting development time by up to two years by enabling "day zero" software development on virtual platforms ?? China's speed & rigor: New players are driving rapid innovation (12-month design to tape-out) without sacrificing quality or safety ?? AI-defined future: Cars are becoming AI-powered. Virtual platforms are crucial for optimizing these complex AI workloads early ?? Security built-in: Security isn't an afterthought. It must be integrated into hardware design from the start, enabled by virtual development ?? System-level thinking: We're moving beyond components to model entire vehicle ecosystems, finding macro-level problems before they become costly Read the full details via the link in our comments!

mPower-ing on to support chip designers and enhance reliability! ?? We announced today that we've collaborated with United Microelectronics Corporation (UMC), a leading global semiconductor foundry, to implement our mPower? software for electromigration (EM) and IR drop analysis, enabling chip designers to optimize performance and enhance reliability. The scalability of mPower enables customers such as UMC to carry out more accurate analysis on larger layouts than ever before and the Transistor-Level Pre-Layout EM and IR Drop capabilities enable early detection of potential issues, allowing designers to optimize chip performance and enhance reliability. ??Key benefits gained with the implementation of mPower at UMC: ? Accelerated time-to-market through industry-leading scalability and rapid verification. ? Enhanced product reliability through early detection and resolution of potential issues. ?? Seamless integration with existing design workflows, enabling comprehensive power analysis. After extensive evaluation, UMC successfully used mPower's automated processes to perform comprehensive SRAM full-chip circuit analysis, delivering precise IR drop distribution assessments and enabling early-stage risk detection. "By integrating Siemens' mPower into our design verification flow, we're enhancing our ability to identify and address potential issues earlier in the development cycle," said Osbert Cheng, vice president of device technology development & design support, UMC. "This aligns perfectly with modern design requirements and helps ensure superior product quality for our customers." Ankur Gupta, our senior vice president and general manager of Digital Design Creation Platform, adds: “Our work with UMC to successfully implement mPower at UMC marks a significant advancement in semiconductor design verification capabilities. As the semiconductor industry addresses the ever-growing challenge of complexity, leaders and pioneers are looking to Siemens’ EDA portfolio to accelerate the design process and help them deliver capable, reliable products to market.” More details in the newsroom - link in comments ??

Up to 75% of chip design projects fall behind schedule ?? One of the biggest culprits: respins caused by incomplete or inaccurate verification. As the industry pushes toward highly specialized SoCs, design complexity is skyrocketing—and so is the pressure to get it right the first time. That’s where metric-driven verification comes in. By focusing on measurable goals—like code coverage and functional coverage—teams can gain a much clearer picture of where their testing stands and what gaps remain. ?? At Siemens, the Veloce Coverage and Assertion App makes this process actionable. It delivers: ??Code coverage insights (statements, branches, toggles, FSMs) ??Functional coverage tracking (coverpoints, covergroups) ??Assertion-based debug (when, where, how often assertions fire) ??Easy visualization of coverage holes and progress With Veloce, verification becomes smarter, more targeted, and more efficient—helping teams avoid costly respins and hit aggressive tape-out schedules. In a fast-moving market, first-pass silicon isn’t just a goal—it’s a business imperative. #Semiconductors #SoCDesign #Verification #EDA?

Another milestone! We are pleased to share that SK keyfoundry (SK?????), in collaboration with Korea Siemens EDA, has launched a 130nm automotive PDK (Process Design Kit) that is exclusively designed for use in Calibre PERC software. This marks a significant milestone as one of the first Korean domestic established node processes to provide not only schematic verification but also layout verification for interconnect reliability. With this new PDK, a wide range of Korean domestic and international fabless companies can leverage SK keyfoundry’s 130nm process to enhance the design optimization of automotive power semiconductors, while at the same time doing more precise reliability verification. “We are thrilled to introduce the Calibre PERC PDK optimized for 130nm automotive power semiconductor processes in collaboration with Siemens EDA. This PDK is designed to improve design efficiency and reliability, providing our customers with a competitive edge in developing high-performance automotive semiconductor products,” said Ilsup Jin, R&D Senior Vice President, SK keyfoundry. “Moving forward, we plan to continue to strengthen our partnership with Siemens to develop next-generation solutions on established node processes.” “We are pleased to support this Calibre PERC PDK for 130nm processes, enabling highly reliable design verification in collaboration with SK keyfoundry. This solution is expected to help differentiate SK keyfoundry in the power semiconductor and IoT markets,” said Junan (JoonHwan) Kim, our General Manager, Siemens EDA Korea. “Siemens remains committed to expanding its collaboration with foundries so that they can leverage the latest EDA technologies regardless of the process nodes they are offering.” Explore the comments to see what SK keyfoundry has planned next. ??

Exciting #news! Arm, a longtime user of Veloce, has selected our Veloce CS for their Neoverse Compute Subsystems verification and validation and has deployed Veloce Strato CS and Veloce proFPGA as part of the design flow for Arm? Neoverse? Compute Subsystems (CSS). "Time to market is increasingly in focus for our partner ecosystem and critical to remaining competitive in this era of computing,” stated Karima Dridi, Head of Productivity Engineering, Arm. “A core component of Arm Neoverse CSS is the pre-validation and verification, made possible by adopting innovative new tools like Siemens Veloce CS system, so that our partners can get their silicon solutions to market faster.” Jean-Marie Brunet, our vice president and general manager, Hardware-Assisted Verification, said, “We are delighted to extend our collaboration with Arm to the Veloce CS system. Veloce Strato CS with the Veloce PCIe Composite Device is delivering outstanding emulation performance improvements with unique and demonstrated capacity scaling, and Veloce proFPGA CS with AMD VP1902 Adaptive SoC is providing a fast and scalable prototyping solution. With the Veloce CS system we address the varied challenges faced by hardware, software, and system engineers. Our longstanding relationship with Arm gives us a strong foundation for gauging their needs and the dynamics of their business as market requirements change.” More details are in the comment section, below ?? #EDA #Verification #Silicon

AI is transforming how electronic design teams manage complexity. ? At #62DAC, we unveiled our AI-enhanced toolset specifically designed for semiconductor and PCB design environments. “We are strategically investing in developing sophisticated industrial-grade AI solutions purpose-built for the unique complexities of EDA,” Mike Ellow, our CEO, said. “Siemens is set to revolutionize the way design teams operate, ushering in a future where generative and agentic AI capabilities are seamlessly integrated into every aspect of the EDA workflow.” Highlights from an exciting week included: ??? Jayne Alexander, representing the Solido Design Environment team, won first place in the poster gladiator battle for presenting the poster “Accelerating chip design with AI-powered additive learning for deep sub-micron technologies” ??? Visitors to our booth enjoyed an immersive digital twin experience by climbing inside a Ford Mach-E car that simulated real driving, brought to life through our PAVE360 platform ?? Our leaders Amit Gupta, Ankur Gupta, AJ Incorvaia, Abhi Kolpekwar and Juan Carlos Rey shared how we're creating industrial-grade AI in EDA powered by NVIDIA in a conversation with John Linford, highlighting how natural language conversations with AI are upending the traditional UX paradigm ?? In panel discussions and interactive demos, we introduced Aprisa AI, which delivers up to 10x productivity gains and improves compute-time efficiency by 3x; Calibre Vision AI, which revolutionizes design verification by enabling faster identification and resolution of critical violations; and Solido AI, which elevates custom IC development through tailored generative and agentic AI capabilities

Dive deep into the evolution of semiconductor design! ?? Join Pratyush Kamal, our Director of R&D for 3D IC Solutions Engineering, as he unravels the complex relationship between microarchitecture and 3D IC design. Key insights include: ? How microarchitecture drives critical data flow decisions ? The shift from siloed to holistic design approaches ? Why tomorrow's 3D ICs demand more than just implementation ? Cross-domain expertise in modern chip design Discover how microarchitecture is reshaping the future of 3D IC technology - the link is in the comments.